ΜΑΡΙΑ ΜΙΧΑΗΛ
ΜΙΧΑΗΛ ΜΑΡΙΑ
MICHAEL MARIA
...
ΑΝΑΠΛΗΡΩΤΗΣ/ΡΙΑ ΚΑΘΗΓΗΤΗΣ/ΡΙΑ
Τμήμα Ηλεκτρολόγων Μηχανικών και Μηχανικών Υπολογιστών
Green Park
Λεωφ. Καλλιπόλεως 75
411
22892277/3454
22892260
www.kios.ucy.ac.cy/mmichael

Προσωπικό Προφίλ

Maria K. Michael holds B.Sc. (summa cum laude) and M.Sc. degrees in Computer Science, and a Ph.D. in Engineering Sciences (specialization in Computer Engineering) from Southern Illinois University, USA. Prior to joining the University of Cyprus, she has taught as a Lecturer at the ECE Department at Southern Illinois University, and as an Assistant Professor of Computer Science and Engineering at the University of Notre Dame, USA. She is currently an Associate Professor with the Electrical and Computer Engineering Department at the University of Cyprus.

Her research expertise falls in the areas of test and reliability of digital circuits and chip-level architectures, with emphasis on state-of-the-art CAD algorithms for automatic testing, diagnosis and verification, as well as fault tolerance and reliability, applicable to large-scale VLSI circuits and reusable embedded cores integrated into whole chip-level architectures and large-scale on-chip multiprocessors. Recent research interests expand to design and optimization of embedded systems and other chip-level architectures, dynamic self-detecting and self-healing architectures, and dependability/reliability /availability in the hardware backbone of the computing continuum, enabling IoT and cyber-physical systems. Current research focuses on dynamic and intelligent state-of-the-art parallel CAD algorithms for automatic testing and fault simulation, embedded and general-purpose multi-/many-core systems reliability and on-line testing, intelligent methods for design, test and fault tolerance, delay test and emerging fault models, and decision diagrams and their applicability in test/diagnosis CAD problems. Her research has been funded by the University of Cyprus, the University of Notre Dame, USA, the Cyprus Research Promotion Foundation, Intel Corporation, and the European Union RTD Framework Programme. Part of her work was nominated for a Best Paper Award, IEEE International Symposium on Quality Electronic Design, 2005, and the Best Dissertation of the Year Award at SIU-C by the College of Engineering, SIU-C in 2002. She is the co-recipient of a Best Paper Award by the IEEE Microelectronics Systems in Education Conference, July 2009.

Between 2009-2013, she co-founded and co-organized the International Workshop on Design for Reliability (DFR), which was held in conjunction with the International Conference on High Performance and Embedded Architectures and Compilers (HiPEAC), aiming to stimulate interest in the emerging and challenging issues of reliability-aware design by bringing together researchers from various areas (design, verification, test, architecture, fault-tolerance and reliability) to share ideas and foment future research in holistic approaches for reliable next-generation computing systems. Between 2011-2015 she was a member of the Management Committee of the EU ICT COST Action on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN) and a Vice-Chair of the MEDIAN workgroup on Dependability evaluation and validation/debug methodologies.

Maria has served on numerous organizing and technical program committees of various conferences. She was Technical Program Chair for the 28th IEEE Annual International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS'15, MA-USA), General Chair of DFTS'16, and General Chair for the 22nd IEEE European Test Symposium (ETS) hosted in Cyprus. She is a member of the IEEE.

         

-      Design & test automation for VLSI circuits and systems

-      Fault tolerance and reliability of digital systems

-      Testing and diagnosis of electronic circuits and systems

-      Design for testability

-      Embedded and general-purpose multi-/many-core systems reliability and on-line test

-      Intelligent methods for design, test and fault tolerance

-      Test-based/semi-formal verification and timing analysis

-      Graph theory and (parallel) algorithms for CAD tools; decision diagrams and SAT

M. Skitsas, C. Nicopoulos and M. K. Michael, “DaemonGuard: Enabling O/S-Orchestrated Fine-Grained Software-Based Selective-Testing in Multi-/Many-Core Microprocessors”, IEEE Transactions on Computers, to appear, published online (IEEE Xplore),DOI Bookmark: 10.1109/TC.2015.2449840, June 2015, pp. 1-14.

M. Maniatakos, M. K. Michael and Y. Makris, “Multiple-Bit Upset Protection in Microprocessor Memory Arrays using Vulnerability-based Parity Optimization and Interleaving”, IEEE Transactions on Very Large Scale Integration, to appear, published online (IEEE Xplore), DOI Bookmark: 10.1109/TVLSI.2014.2365032, November 2014, pp. 1-13.

H. Kim, S. B. Boga, A. Vitkovskiy, S. Hadjitheophanous, P. V. Gratz, V. Soteriou and M. K. Michael, “Use it or Lose it: Proactive, Deterministic Longevity in Future Chip Multiprocessors, ACM Transactions on Design Automation of Electronic Systems, Vol. 20, No. 4, September 2015, pp. 1-26.

M. Maniatakos, M. K. Michael, C. Tirumurti and Y. Makris, "Revisiting Vulnerability Analysis in Modern Microprocessors", IEEE Transactions on Computers, Vol. 64, No. 9, September 2015, pp. 2664-2674.

M. Ottavi, S. Pontarelli, D. Gizopoulos, C. Bolchini, M. K. Michael, L. Anghel, M. Tahoori, A. Paschalis, P. Reviriego, O. Bringmann, V. Izosimov, H. Manhaeve, C. Strydis, S. Hamdioui, “Dependable Multicore Architectures at Nanoscale: the view from Europe”, IEEE Design & Test, Vol. 32, No. 2, April 2015, pp. 17-28.

 

S. Neophytou and M. K. Michael, “Multiple detection test generation with diversified fault partitioning paths”, Microprocessors and Microsystems - Embedded Hardware Design (MICPRO), Vol. 38, No. 6, August 2014, pp. 585-597.

 

S. Neophytou, C. Christou, and M. K. Michael, “A Non-Enumerative Technique for Measuring Path Correlation in Digital Circuits”, Journal of Electronic Testing: Theory and Applications (JETTA), Vol.28, No. 6, October 2012, pp. 843-856.

 

C. Ttofis, T. Theocharides, and M. K. Michael, “FPGA-based Laboratory Assignments for NoC-based Manycore Systems”, IEEE Transactions on Education, Vol. 55, No. 2, May 2012, pp. 180-189.

 

S. Neophytou and M. K. Michael, “Test Pattern Generation for Relaxed n-detect Test Sets”, IEEE Transactions on Very Large Scale Integration (VLSI), Vol. 20, No. 3, March 2012, pp. 410-423.

 

R. Adapa, S. Tragoudas, and M. K. Michael, “Improved Diagnosis Using Enhanced Fault Dominance Relations", Integration, the VLSI Journal, Vol. 44, No. 3, June 2011, pp. 217-228.

 

C. Tofis, A. Papadopoulos, T. Theocharides, M. K. Michael, and D. Doumenis, "An MPSoC-based QAM Modulation Architecture with Run-Time Load-Balancing", EURASIP Journal of Embedded Systems, Vol. 2011 (2011), Article ID 790265, 15 pages.

 

T. Theocharides, M. K. Michael, M. Polycarpou, and A. Dingankar, “Hardware-Enabled Dynamic Resource Allocation for Manycore Systems using Bidding-based System Feedback”, EURASIP Journal on Embedded Systems, Vol. 2010 (2010), Article ID 261434, 21 pages.

 

S. Neophytou and M. K. Michael, “Test Set Generation With a Large Number of Unspecified Bits Using Static and Dynamic TechniquesIEEE Transactions on Computer, Vol. 59, No. 3, March 2010, pp. 301-316.

 

K. Christou, M. K. Michael and S. Tragoudas, “On the use of ZBDDs for Implicit and Compact Critical Path Delay Fault Test Generation”, Journal of Electronic Testing: Theory and Applications (JETTA), Vol.24, No. 1 – 3, June 2008, pp. 203-222.

S. Neophytou, M. K. Michael, and S. Tragoudas, “Functions for Quality Transition Fault Tests and their Applications in Test Set Enhancement", IEEE Transactions on Computer-Aided Design (CAD) of Integrated Circuits and Systems, Vol. 25, No. 12, December 2006, pp. 3026-2035.

M. K. Michael and S. Tragoudas, “Function-based Compact Test Pattern Generation for Path Delay Faults”, IEEE Transactions on Very Large Scale Integration (VLSI), Vol. 13, No. 8, August 2005, pp. 996-1001.

M. K. Michael, T. Haniotakis, and S. Tragoudas, “A Unified Framework for Generating Propagation Functions for Logic Errors and Events", IEEE Transactions on Computer-Aided Design (CAD) of Integrated Circuits and Systems, Vol. 23, No. 6, June 2004, pp. 980-986.

S. Padmanaban, M. K. Michael, and S. Tragoudas, “Exact Path Delay Fault Coverage with Fundamental Zero-Suppressed BDD Operations”, IEEE Transactions on Computer-Aided Design (CAD) of Integrated Circuits and Systems, Vol. 22, No. 3, March 2003, pp. 305-316.

M. K. Michael and S. Tragoudas, “ATPG Tools for Delay Faults at the Functional level”, ACM Transactions On Design Automation of Electronic Systems (TODAES), Vol. 7, Issue 1, January 2002, pp. 33-57.

Profile Information

Maria K. Michael holds B.Sc. (summa cum laude) and M.Sc. degrees in Computer Science, and a Ph.D. in Engineering Sciences (specialization in Computer Engineering) from Southern Illinois University, USA. Prior to joining the University of Cyprus, she has taught as a Lecturer at the ECE Department at Southern Illinois University, and as an Assistant Professor of Computer Science and Engineering at the University of Notre Dame, USA. She is currently an Associate Professor with the Electrical and Computer Engineering Department at the University of Cyprus.

Her research expertise falls in the areas of test and reliability of digital circuits and chip-level architectures, with emphasis on state-of-the-art CAD algorithms for automatic testing, diagnosis and verification, as well as fault tolerance and reliability, applicable to large-scale VLSI circuits and reusable embedded cores integrated into whole chip-level architectures and large-scale on-chip multiprocessors. Recent research interests expand to design and optimization of embedded systems and other chip-level architectures, dynamic self-detecting and self-healing architectures, and dependability/reliability /availability in the hardware backbone of the computing continuum, enabling IoT and cyber-physical systems. Current research focuses on dynamic and intelligent state-of-the-art parallel CAD algorithms for automatic testing and fault simulation, embedded and general-purpose multi-/many-core systems reliability and on-line testing, intelligent methods for design, test and fault tolerance, delay test and emerging fault models, and decision diagrams and their applicability in test/diagnosis CAD problems. Her research has been funded by the University of Cyprus, the University of Notre Dame, USA, the Cyprus Research Promotion Foundation, Intel Corporation, and the European Union RTD Framework Programme. Part of her work was nominated for a Best Paper Award, IEEE International Symposium on Quality Electronic Design, 2005, and the Best Dissertation of the Year Award at SIU-C by the College of Engineering, SIU-C in 2002. She is the co-recipient of a Best Paper Award by the IEEE Microelectronics Systems in Education Conference, July 2009.

Between 2009-2013, she co-founded and co-organized the International Workshop on Design for Reliability (DFR), which was held in conjunction with the International Conference on High Performance and Embedded Architectures and Compilers (HiPEAC), aiming to stimulate interest in the emerging and challenging issues of reliability-aware design by bringing together researchers from various areas (design, verification, test, architecture, fault-tolerance and reliability) to share ideas and foment future research in holistic approaches for reliable next-generation computing systems. Between 2011-2015 she was a member of the Management Committee of the EU ICT COST Action on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN) and a Vice-Chair of the MEDIAN workgroup on Dependability evaluation and validation/debug methodologies.

Maria has served on numerous organizing and technical program committees of various conferences. She was Technical Program Chair for the 28th IEEE Annual International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS'15, MA-USA), General Chair of DFTS'16, and General Chair for the 22nd IEEE European Test Symposium (ETS) hosted in Cyprus. She is a member of the IEEE.

-      Fault tolerance and reliability of digital systems

-      Test automation and diagnosis of electronic circuits and systems

-      Design for testability

-      Embedded and general-purpose multi-/many-core systems reliability and on-line test

-      Intelligent methods for design, test and fault tolerance

-      Test-based/semi-formal verification and timing analysis

-      Graph theory and (parallel) algorithms for CAD tools; decision diagrams and SAT

M. Skitsas, C. Nicopoulos and M. K. Michael, “DaemonGuard: Enabling O/S-Orchestrated Fine-Grained Software-Based Selective-Testing in Multi-/Many-Core Microprocessors”, IEEE Transactions on Computers, to appear, published online (IEEE Xplore),DOI Bookmark: 10.1109/TC.2015.2449840, June 2015, pp. 1-14.

M. Maniatakos, M. K. Michael and Y. Makris, “Multiple-Bit Upset Protection in Microprocessor Memory Arrays using Vulnerability-based Parity Optimization and Interleaving”, IEEE Transactions on Very Large Scale Integration, to appear, published online (IEEE Xplore), DOI Bookmark: 10.1109/TVLSI.2014.2365032, November 2014, pp. 1-13.

H. Kim, S. B. Boga, A. Vitkovskiy, S. Hadjitheophanous, P. V. Gratz, V. Soteriou and M. K. Michael, “Use it or Lose it: Proactive, Deterministic Longevity in Future Chip Multiprocessors, ACM Transactions on Design Automation of Electronic Systems, Vol. 20, No. 4, September 2015, pp. 1-26.

M. Maniatakos, M. K. Michael, C. Tirumurti and Y. Makris, "Revisiting Vulnerability Analysis in Modern Microprocessors", IEEE Transactions on Computers, Vol. 64, No. 9, September 2015, pp. 2664-2674.

M. Ottavi, S. Pontarelli, D. Gizopoulos, C. Bolchini, M. K. Michael, L. Anghel, M. Tahoori, A. Paschalis, P. Reviriego, O. Bringmann, V. Izosimov, H. Manhaeve, C. Strydis, S. Hamdioui, “Dependable Multicore Architectures at Nanoscale: the view from Europe”, IEEE Design & Test, Vol. 32, No. 2, April 2015, pp. 17-28.

 

S. Neophytou and M. K. Michael, “Multiple detection test generation with diversified fault partitioning paths”, Microprocessors and Microsystems - Embedded Hardware Design (MICPRO), Vol. 38, No. 6, August 2014, pp. 585-597.

 

S. Neophytou, C. Christou, and M. K. Michael, “A Non-Enumerative Technique for Measuring Path Correlation in Digital Circuits”, Journal of Electronic Testing: Theory and Applications (JETTA), Vol.28, No. 6, October 2012, pp. 843-856.

 

C. Ttofis, T. Theocharides, and M. K. Michael, “FPGA-based Laboratory Assignments for NoC-based Manycore Systems”, IEEE Transactions on Education, Vol. 55, No. 2, May 2012, pp. 180-189.

 

S. Neophytou and M. K. Michael, “Test Pattern Generation for Relaxed n-detect Test Sets”, IEEE Transactions on Very Large Scale Integration (VLSI), Vol. 20, No. 3, March 2012, pp. 410-423.

 

R. Adapa, S. Tragoudas, and M. K. Michael, “Improved Diagnosis Using Enhanced Fault Dominance Relations", Integration, the VLSI Journal, Vol. 44, No. 3, June 2011, pp. 217-228.

 

C. Tofis, A. Papadopoulos, T. Theocharides, M. K. Michael, and D. Doumenis, "An MPSoC-based QAM Modulation Architecture with Run-Time Load-Balancing", EURASIP Journal of Embedded Systems, Vol. 2011 (2011), Article ID 790265, 15 pages.

 

T. Theocharides, M. K. Michael, M. Polycarpou, and A. Dingankar, “Hardware-Enabled Dynamic Resource Allocation for Manycore Systems using Bidding-based System Feedback”, EURASIP Journal on Embedded Systems, Vol. 2010 (2010), Article ID 261434, 21 pages.

 

S. Neophytou and M. K. Michael, “Test Set Generation With a Large Number of Unspecified Bits Using Static and Dynamic TechniquesIEEE Transactions on Computer, Vol. 59, No. 3, March 2010, pp. 301-316.

 

K. Christou, M. K. Michael and S. Tragoudas, “On the use of ZBDDs for Implicit and Compact Critical Path Delay Fault Test Generation”, Journal of Electronic Testing: Theory and Applications (JETTA), Vol.24, No. 1 – 3, June 2008, pp. 203-222.

S. Neophytou, M. K. Michael, and S. Tragoudas, “Functions for Quality Transition Fault Tests and their Applications in Test Set Enhancement", IEEE Transactions on Computer-Aided Design (CAD) of Integrated Circuits and Systems, Vol. 25, No. 12, December 2006, pp. 3026-2035.

M. K. Michael and S. Tragoudas, “Function-based Compact Test Pattern Generation for Path Delay Faults”, IEEE Transactions on Very Large Scale Integration (VLSI), Vol. 13, No. 8, August 2005, pp. 996-1001.

M. K. Michael, T. Haniotakis, and S. Tragoudas, “A Unified Framework for Generating Propagation Functions for Logic Errors and Events", IEEE Transactions on Computer-Aided Design (CAD) of Integrated Circuits and Systems, Vol. 23, No. 6, June 2004, pp. 980-986.

S. Padmanaban, M. K. Michael, and S. Tragoudas, “Exact Path Delay Fault Coverage with Fundamental Zero-Suppressed BDD Operations”, IEEE Transactions on Computer-Aided Design (CAD) of Integrated Circuits and Systems, Vol. 22, No. 3, March 2003, pp. 305-316.

M. K. Michael and S. Tragoudas, “ATPG Tools for Delay Faults at the Functional level”, ACM Transactions On Design Automation of Electronic Systems (TODAES), Vol. 7, Issue 1, January 2002, pp. 33-57.